AR# 18897


6.1i ECS - Mixed VHDL, Verilog, schematic project fails with NGDBUILD 604 error


Keywords: Mixed, Verilog, vhdl, schematic, flow, instantiated, sch2vhdl, symbol, ngdbuild, logical block, case, sensitive

Urgency: Standard

General Description:
If a Verilog module is instantiated as a schematic symbol in mixed language design and the 'Generated Simulation Language' is set to VHDL, NGDBUILD may fail with the following error:

"ERROR:NgdBuild:604 - logical block '<Instance_name>' with type '<module_name>' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'control_logic' is not supported in target '<target_family>'."


This happens if the Verilog module contains any capital letters. The symbol for the Verilog module is correctly created and added to the schematic file. However, sch2vhdl does not retain capitalization when the intermediate ".vhf" is written out. Therefore, since Verilog is case sensitive, the synthesis tool looks for the module name with all lower case letters. Because the module does not exist with all lower case letters, the synthesis tool creates a black box for the component. NGDBUILD then fails because there is not a netlist to match black box.

There are three ways to work around this problem:

1. Rename the Verilog module to use all lowercase letters. Re-synthesize, and the module should be picked up correctly.
2. Change the 'Generated Simulation Language' to Verilog. Sch2verilog will be run instead of sch2vhdl, and the module case will be correctly maintained.
3. Edit the intermediate "<schematic_name>.vhf" file and change the module declaration to the proper case. Note that this is a short-term work-around as the "<schematic_name>.vhf" file will be re-written before synthesis if the schematic file has been touched.
AR# 18897
日期 01/08/2006
状态 Archive
Type 综合文章
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