When I run a timing simulation on an SPI-4.2 static alignment core, the following warnings are reported:
# ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.372 ns; Observed := 0.306 ns; At : 804.102 ns
# Time: 804102 ps Iteration: 3 Instance: /pl4_tstbench/pl4_top_lb0/pl4_snk_top1_pl4_snk_io0_staticalign_chan_gen_chan_gen_2_ddr1_gen_ddr1_gen_chan1_gen_dr"
"# ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.365 ns; Observed := 0.357 ns; At : 808.368 ns
# Time: 808368 ps Iteration: 3 Instance:
Also, the Sink core does not go in frame and the SnkBusErr and SnkBusErrStat(3) is asserted, flagging DIP4 errors on training patterns or idles.
To avoid these warnings, modify the PHASE_SHIFT value of the DCM instance in your UCF:
INST "pl4_snk_top0/pl4_snk_clk0/LowFreq.StaticAlign_StaticAlign.rdclk_dcm0" PHASE_SHIFT = 25;
Modify this such that the clock is aligned to the middle of the data eye when it reaches the DDR flip-flops. This will then prevent the warnings and SnkBusErr and SnkBusErrStat(3) assertions before going in frame.
Once the simulation is complete and you are ready to download the design into the device, you may need to modify the PHASE_SHIFT value again after finding the optimal PHASE_SHIFT for your device. Please see (Xilinx Answer 16112) for more information.