This README contains the Release Notes for the 6.1.1 System Generator for DSP. The Release Notes include a list of the issues that are fixed by this Release.
Why does the clock probe have a phase offset? (Xilinx Answer 18957).
Where can I obtain the "spram.mdl" that is missing from the System Generator for DSP 6.1 installation? (Xilinx Answer 18830).
Why does the black box cause MATLAB to hang when there are more than ten output ports? (Xilinx Answer 18912).
Why do I get a PERL error for JTAG hardware in the loop if there are spaces in the full path to the support package files? (Xilinx Answer 18958).
Why do I occasionally get errors from some of my binary files that were generated? (Xilinx Answer 18959).
Why do I see unexpected results when using the XtremeDSP ZBTRAM with my hardware in the loop simulation? (Xilinx Answer 18960).
Why is the IR length for the Virtex-II incorrect in the JTAG section of the System Generator documentation? (Xilinx Answer 18961).
The "conv_pkg.vhd" is not included in the black box instantiation wrapper. Why? (Xilinx Answer 18962).
Why does VHDL generation fail when an output is connected to a scope? (Xilinx Answer 18963).
Why does my multi-rate design require a System Generator token at the top level? (Xilinx Answer 18976).
How do I install System Generator 6.1.1 with ISE 6.2i? (Xilinx Answer 18964).
What are the known issues for System Generator v6.1.1? (Xilinx Answer 18954).