AR# 18957


6.1.1 System Generator for DSP - Why does the clock probe have a phase offset?


General Description: 

The SysGen Clock Probe block has a forced phase offset that causes the clock to transition slightly before XFix data transitions. This offset was originally added to assist visual analysis. Its inclusion has caused problems with the fixed-step solver and also in applications that assume the rising edge coincides with data transitions.


This has been fixed in System Generator 6.1.1.

AR# 18957
日期 05/16/2014
状态 Archive
Type 综合文章
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