AR# 18987


LogiCORE SPI-4.2 (POS-PHY L4) v6.1 - When I run a simulation on the Verilog demonstration testbench, RDat becomes "x" and SnkFFPayloadErr is flagged


General Description: 

When I simulate the Verilog demo testbench for the SPI4.2 v6.1 core, the testbench stimulus module sends "x" on bits "0" to "11" on RDat. This occurs when RDat is transmitting payload control words. The core reacts to this behavior by flagging the SnkFFPayloadErr signal.


This occurs only when the user generates the core by choosing the "Number of Channels" option to be "1" in the GUI.  


To work around this issue, select a number other than "1" for the "Number of Channels" value and re-generate the core. You can still choose the calendar length value to be "1" to observe the behavior of the core in a 1-channel configuration. 


This issue will be fixed in a future release of the SPI4.2 core.

AR# 18987
日期 05/16/2014
状态 Archive
Type 综合文章
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