UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18997

LogiCORE MII to RMII Core - Are there any timing constraints required for the MII to RMII core?

描述

Urgency: Standard

General Description:

Are there any timing constraints required for the MII to RMII shim core?

解决方案

The only constraint that is needed is to constrain Ref_Clk to 50 MHz. The constraint should look as follows:

NET Ref_Clk TNM_NET = Ref_Clk;

TIMESPEC TS_Ref_Clk = PERIOD Ref_Clk 50 MHz HIGH 50 %;

This will be documented in a future version of the data sheet.

AR# 18997
日期 12/15/2012
状态 Active
Type 综合文章
的页面