We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19031

6.2i PACE - Assigning improper constrains for bi-directional pads causes "ERROR:NgdBuild:755..."


Keywords: ISE, 6.2, pin, constraint, Synplify, CPLD

Urgency: Standard

General Description:
If I use Synplify as a synthesis tool to synthesize a CPLD design and then use PACE to assign the package pins, the pin assignment for bi-directional I/Os causes the following errors in NGDBuild:

"ERROR:NgdBuild:755 - Line 1 in 'ucf_name.ucf': Could not find net(s) 'net_name_pad(0)' in the design."

How do I fix this?


The error is caused by PACE reading the logical_primitive name instead of the I/O name for the bi-directional pad. For example, BI_DATA_pad(3) vs BI_DATA(3). Therefore, the pin assignment constraints generated by PACE will have " _pad" appended into the bi-directional I/O name. The " _pad" causes a mismatch when NGDBuild compiles the netlist that lead to the NGDBuild error.

Currently, to work around this issue, manually remove "_pad" section of the I/O name in the UCF file after using PACE to do the pin assignment for the bi-directional I/Os.

NOTE: This issue occurs only when targeting CPLD design using Synplify to synthesize the design and the design contains bi-directional I/Os.
AR# 19031
日期 03/27/2007
状态 Archive
Type 综合文章