When I try to load a design for Verilog simulation, the following error occurs:
"ERROR: ../<project>/<module.v>: Unresolved reference to 'glbl' in 'glbl.GSR'"
This problem occurs only when "generate" statements are used with MXE 5.7c. If the "generate" statement is not used in the code, refer to (Xilinx Answer 6537) for information on how to use the "glbl.v" module in Verilog simulations. The "generate" statement is part of the Verilog-2001 standards. This error occurs because support for Verilog-2001 was relatively new in 5.7c.
The best way to work around this issue is to not use "generate" statements in this version of MXE.