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AR# 19130

6.1i DCM, Simulation - Period violations occur after 289 ms


Keywords: DCM, simulation, timing, violation, error, input, clock, period, 289042813.520, 289, ms

Urgency: Standard

General Description:
When using the 6.1i DCM model, if you simulate for more than 289ms, the following violations occur on every rising edge of the clock:

"Timing Violation Error : Input clock period of, 289042813.520 ns, on the B@
port of instance TC_TOP.tb_top.dut.CLK_GEN.DCM_CLK179.i_max_clkin exceeds
allotted value of 289042811.214 ns at simulation time 289042819.107 ns."


This problem is fixed in the 6.2i software. After installing 6.2i, recompile the simulation models and this will error will no longer occur.
AR# 19130
日期 11/18/2008
状态 Archive
Type 综合文章