When using Xilinx SPI4.2 device with Vitesse Framer, you might run into following issues. The Vitesse part that is known to have problem is VSC9118. There might be others.
The following issues are known regarding Vitesse VSC9118 Framer:
1. Does not receive periodic training patterns correctly, must be turned off at Source side (Xilixn FPGA)
2. Does not receive source sync data/clock correctly, needs clock or data phase shift to occur at Source side.
To work around the above two issues:
1. Turn off sending of periodic training by setting xilinx SPI4.2 Source Core Static configuration setting:
DataMaxT[15:0] or AlphaData[7:0] to zero.
These settings can be found in SPI4.2 Core Generation GUI.
2. To work around the source synchronous issue, please contact Xilinx Technical Support and open a WebCase. Networking IP experts will be able to assist you with this.