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AR# 1923

ModelSim - How do I compile the 1.5 SimPrim, LogiBLOX, UniSim, and CORE Generator HDL libraries?


Keywords: SIMPRIM, LogiBLOX, UNISIM, VHDL, Verilog, ModelSim, Vsim, compile, library, XUL, Vcom, Vlog

Urgency: Standard

General Description:
To perform timing or post-synthesis functional HDL simulation in M1, the Verilog and/or VHDL (VITAL) SimPrim models must be compiled for use in the Model Technology simulator. If instantiated LogiBLOX and/or Unified library components are to be behaviorally simulated, the LogiBLOX and/or UniSim libraries must be compiled, as well.

This Answer Record is written for the ModelSim versions 5.1x for Workstations, or 4.7x for PCs. It applies to earlier versions of the simulator if the word MODELSIM is replaced with V-SYSTEM.

Please see (Xilinx Answer 2561) for information on how to compile the HDL libraries for Xilinx Alliance 2.1.



A TCL script is available on Xilinx FTP site. Currently, this script can only be used with the ModelSim EE/PE edition.

NOTE: You must use the xilinx_lib.tcl script for ModelSim EE, and xilinx_lib.tcl for ModelSim PE.




Use the "source" command from the ModelSim prompt to load that TCL/TK code. At the ModelSim prompt, type MODELSIM> source <path_to_script>/xilinx_lib.tcl.


Set the environment variable MODELSIM_TCL to the name of the script (xilinx_lib.tc_) prior to invoking ModelSim. (NOTE: MODELSIM_TCL can be a list of TCL/TK files to load, separated with ":" symbols.)

MODELSIM_TCL <path_to_script>/xilinx_lib.tcl

where <path_to_script> is the path name for the directory to where the script was saved.


The Xilinx Alliance software contains 3 types of HDL simulation libraries, and CORE Generator contains one:

SIMPRIM - Library of generic simulation primitives
LogiBLOX - Library of LogiBLOX simulation models (VHDL only)
UNISIM - Library of Unified component simulation models (A1.4+) XUL - CORE Generator VHDL Library containing arithmetic functions

The instructions that follow refer to the following variables:

VERILOG_DESTN - Location for compiled Verilog libraries
(Example setting: $MODEL_TECH/xilinx/verilog)

VHDL_DESTN - Location for compiled VHDL libraries
(Example setting: $MODEL_TECH/xilinx/vhdl)

If you want logical library names to be available for all designs, set your MODELSIM environment variable to the location of your master .ini file:

For Example
setenv MODELSIM $MODEL_TECH/Xilinx/modelsim.ini

If MODELSIM is not set when Vmap is run, the logical library mapping is done locally; therefore, all Vmap commands would have to be run for each new HDL design.

For Verilog users, the compilation commands that need to be executed are:

SIMPRIM (A1.4, 1.5 and 1.5i)

vlib $VERILOG_DESTN/simprims
vmap simprims_ver $VERILOG_DESTN/simprims
vlog -work simprims_ver $XILINX/verilog/src/simprims/*.vmd


(none required)

UNISIM (Versions A1.4 and later)

vlib $VERILOG_DESTN/uni3000
vmap uni3000 $VERILOG_DESTN/uni3000
vlog -work uni3000 $XILINX/verilog/src/UNI3000/*.v

vlib $VERILOG_DESTN/uni4000e
vmap uni4000e $VERILOG_DESTN/uni4000e
vlog -work uni4000e $XILINX/verilog/src/UNI4000E/*.v

vlib $VERILOG_DESTN/uni4000x
vmap uni4000x $VERILOG_DESTN/uni4000x
vlog -work uni4000x $XILINX/verilog/src/UNI4000X/*.v

vlib $VERILOG_DESTN/uni5200
vmap uni5200 $VERILOG_DESTN/uni5200
vlog -work uni5200 $XILINX/verilog/src/UNI5200/*.v

vlib $VERILOG_DESTN/uni9000
vmap uni9000 $VERILOG_DESTN/uni9000
vlog -work uni9000 $XILINX/verilog/src/UNI9000/*.v

vlib $VERILOG_DESTN/unispartan
vmap unispartan $VERILOG_DESTN/unispartan
vlog -work unispartan $XILINX/verilog/src/UNISPARTAN/*.v

vlib $VERILOG_DESTN/unispartanxl
vmap unispartanxl $VERILOG_DESTN/unispartanxl
vlog -work unispartanxl $XILINX/verilog/src/UNISPARTANXL/*.v

vlib $VERILOG_DESTN/univirtex
vmap univirtex $VERILOG_DESTN/univirtex
vlog -work univirtex $XILINX/verilog/src/UNIVIRTEX/*.v

(NOTE: To reference these libraries during Verilog simulation, the -L switch must be specified during VSIM execution, specifying the library name given for the VMAP command.)

Example for Verilog timing simulation:

vlog testbench.v time_sim.v
vsim -L simprims_ver testbench_module_name

For VHDL users, the commands are:


vlib $VHDL_DESTN/simprim
vmap simprim $VHDL_DESTN/simprim
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd
vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd


vlib $VHDL_DESTN/logiblox
vmap logiblox $VHDL_DESTN/logiblox
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlutil.vhd
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlarith.vhd
vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/logiblox.vhd

UNISIM (Versions A1.4 and later)

vlib $VHDL_DESTN/unisim
vmap unisim $VHDL_DESTN/unisim
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd

vlib $VHDL_DESTN/unisim_5k
vmap unisim_5k $VHDL_DESTN/unisim_5k
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCOMP52K.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL52K.vhd
vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCFG52K.vhd

CORE Generator (COREGen must be installed separately from M1)

vlib $VHDL_DESTN/xul
vmap xul $VHDL_DESTN/xul
vcom -work xul $COREGEN/ip/xilinx/xul/ul_utils.vhd

(NOTE: $COREGEN refers to the location in which CORE Generator was installed on the system.)
AR# 1923
日期 01/30/2002
状态 Archive
Type ??????