During gate-level or timing simulation of a FIFO Generator core in Verilog, following error occurs:
"# ** Error: /Xilinx/verilog/src/simprims/X_FF.v(43): $recovery( negedge SET:693111881 ps, posedge CLK &&& (set_clk_enable == 1):693112014 ps, 768 ps ); FAIL_TIME: 693112014ps"
This Verilog SimPrim error may be safely ignored.
This error is due to the flip-flops within the FIFO that are expected to violate setup/hold times. Although Async_Reg attributes are appropriately assigned to these flip-flops, the error still occurs. The FIFO Generator core is designed such that no functional or timing errors will be affected by this violation.