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AR# 19385

OPB/PLB DDR - How do I determine EDK DDR controller timing?

描述

General Description:

How do I perform a board-level timing analysis on a design utilizing an EDK DDR controller?

解决方案

See the following PDF file for an example analysis:

(Xilinx File http://www.xilinx.com/txpatches/pub/applications/misc/ar19385.pdf)

AR# 19385
日期 12/15/2012
状态 Active
Type 综合文章
的页面