We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
General Description: The first two bytes to be loaded in parallel configuration are FF 20. If the data is viewed this way, is D7 the MSB or LSB? (D7 .. D0 refer to the parallel configuration data pins on the FPGA.)
D0 is the MSB and D7 is the LSB.
Therefore, the second byte loaded to D7...D0 of the FPGA would look like:
The data book will refer to D0 as the LSB in some cases, as that is how the data is organized internally for the FPGA. To ensure that the configuration data is being presented in the proper order, use the example above.