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AR# 1943

Concept - CAPSLOCK_OFF and its effect on translation of lower-cased pin name properties

Description

Keywords: Concept, translate, property, case sensitive, upper, lower, caps_lock,
timespec, timegrp

Urgency: Standard

General Description:
Case sensitivity issues may cause problems when translating
timing specifications in a Concept schematic. In the M1
release, it is recommended that the capslock_off setting be
enabled to properly translate TIMEGRP names, but this may
cause some side effects as well.

Consider that the xilinx.pff file is a data file listing all
properties that should be translated from a Concept schematic,
and the matching of properties found in the schematic
actually becomes case sensitive when capslock_off is turned
on.

When you set the capslock_off variable, properties
you enter in your schematic no longer get converted to
uppercase (the default behavior in Concept):
==============================================================

Suppose you have the following entries in your xilinx.pff file
(note the variations in case):

ts01: "ts01" String NORMAL; {Timespec}
TS02: "ts02" String NORMAL;
ts03: "TS03" String NORMAL;
TS04: "TS04" String NORMAL;
TS05: "TS05" String NORMAL;

The first column corresponds to the NAME of the property,
while the second column corresponds to the OUTPUT FORMAT of
the property when written out to the EDIF netlist.

This is what you will see in the .EDF netlist written by
concept2xil:
-------------------------------------------------
(property ts01 (string "dc2s=20ns")
(property TS03 (string "from:pads:to:pads:30ns")


Note that TS02, TS04, and TS05 are missing from the .edf file


In the schematic file, logic.1.1, you may see the following:
-------------------------------------------------------

FORCEPROP 2 LAST TS01 dc2s=20ns
FORCEPROP 2 LAST TS02 DP2P=30ns
FORCEPROP 2 LAST TS03 from:pads:to:pads:30ns
FORCEPROP 2 LAST TS04 from:ffs:to:pads:20ns
FORCEPROP 2 LAST TS05 from:pads:to:ffs:20ns



解决方案



1. Regardless of how you enter the NAME of a property value in
Concept, it will always get converted to upper case in the
schematic.

2. Keeping caplocks_off preserves the case of the property VALUE only.

3. For the property to be translated to EDIF, its NAME must be
in LOWER case in the 1st column of xilinx.pff. If it is in
UPPER case, it will not get translated because the netlister
will not find a match in the xilinx.pff file with what is
written out to the logic drawing (schematic file).

4. The 2nd column of the xilinx.pff file determines
how the property will look when it is written to the .EDF
file.

- If it is UPPER case in the 2nd column, it will get
written out in UPPER case in the .EDF file

- If it is LOWER case in the 2nd column, it will get
written out in LOWER case in the .EDF file.

The above is true regardless of whether the property is a
pre-defined, or a user-defined property
AR# 1943
创建日期 08/31/2007
Last Updated 02/11/2001
状态 Archive
Type ??????