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AR# 19448

7.1i XST - How do I use the `ifdef to skip embedded meta-comments in the Verilog code?

描述

Keywords: XST, ifdef, synthesis, directive, preprocess

XST processes all synthesis directives, regardless of whether they are enclosed within an `ifdef `endif pair, as in the following example:

`ifdef my_define

// synthesis attribute iostandard of my_port is LVCMOS33;

`endif

How can I embed meta-comments in the `ifdef `endif pair?

解决方案

Currently, it is not possible to embed meta-comments inside of `ifdef `endif constructs. One possible way to work around this issue is to use the new Verilog 2001 attribute passing as follows:

`ifdef my_define

(* iostandard = "LVCMOS33" *)
input my_port;

`endif

Refer to the XST User Guide for more information on Verilog 2001 attribute passing:
http://support.xilinx.com/support/sw_manuals/xilinx6/index.htm.
AR# 19448
日期 01/07/2009
状态 Archive
Type 综合文章
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