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AR# 19480

6.2 System Generator for DSP - Is it possible to use an asynchronous clock inside the SysGen system?

描述

General Description:

Is it possible to use an asynchronous clock inside the SysGen system?

解决方案

For information on this issue, refer to the "Generating Multiple Cycle-True Islands for Distinct Clocks" section in the Xilinx System Generator v6.2 User Guide at:

http://www.xilinx.com/products/software/sysgen/app_docs/user_guide_Chapter_7_Section_2.htm

AR# 19480
日期 12/15/2012
状态 Active
Type 综合文章
的页面