Consider the following scenario where the core is an initiator performing a write transaction:
- PCI-X core starts a mem write.
- Half-way through, initiator de-asserts REQ#.
- Arbiter continues to assert GNT# (PCI-X core is now "parked on").
- Initiator completes the transaction.
The decisions to be made at this point are:
- Return to bus idle, wait four clocks, and then drive AD.
- Immediately drive AD after the initiator completes, because core is "parked on."
In section 4.1.1 of the specification, the following is stated:
"If GNT# is asserted and the bus is idle for four consecutive clocks, the device must actively drive the bus (AD[31::0] and C/BE[3::0]#) no later than the sixth clock and PAR or ECC[6::0] one clock later."
The PCI-X core drives AD[31::0] and C/BE[3::0] immediately instead of waiting for four clock cycles. Is this a problem?
For clarification Xilinx contacted the PCI-X SIG technical support group to ensure that the core's behavior is correct. They confirmed that the correct option above is the one in which the PCI-X core immediately drives AD[31:0] and CBE[3:0] followed by PAR one cycle later after the initiator completes the transaction.
Section 4.1.1 in the PCI-X PT 2.0a specification states that for PCI-X Mode 1, as in a conventional PCI, if no initiators request the bus, the arbiter is permitted to park the bus in PCI-X Mode 1 at any initiator that is capable of being an initiator to prevent the bus signals from floating. It further states that if GNT# is asserted and the bus is idle for four consecutive clocks, the device must actively drive the bus (AD[31::0] and C/BE[3::0]#) no later than the sixth clock and PAR or ECC[6::0] one clock later.
In the scenario mentioned above, since the PCI-X core is completing a current transaction and GNT# is still asserted (no change in bus ownership), the core should continue driving the bus. There is no need to stop driving the bus before driving the bus again.