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AR# 19499

6.2 System Generator for DSP - Why is there a PicoBlaze simulation mismatch during the first clock cycle when the first instruction is arithmetic or logical?

描述

General Description: 

Why is there a PicoBlaze simulation mismatch during the first clock cycle when the first instruction is arithmetic or logical?

解决方案

This is a known issue in System Generator for DSP 6.2 and will be fixed in System Generator for DSP 6.3. 

 

The mismatch occurs only for the first clock cycle (first time step) if the instruction is arithmetic or logical. 

 

The simulation starts as if there were a register, but since there is not a register, when you perform the VHDL simulation, a mismatch occurs for the first clock cycle.

AR# 19499
日期 05/16/2014
状态 Archive
Type 综合文章
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