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AR# 19542

7.1i Timing Analyzer Virtex-4 - Paths through IDELAY are not analyzed

描述

General Description:

The timing report is not reporting any paths through the IDELAY or ILOGIC components of my design.

解决方案

This is scheduled to be fixed in the next major release of the design tools.

AR# 19542
日期 01/18/2010
状态 Archive
Type 综合文章
的页面