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AR# 19546

8.1i CPLD CPLDFit - Period timing constraint fails to analyze register to clock enable path

描述

General Description: 

A period timing constraint does not cover the path from a register to a downstream register's clock enable.

解决方案

Use the following URL to open a WebCase to have Xilinx Technical Support evaluate the path in question: 

http://support.xilinx.com/support/clearexpress/websupport.htm

AR# 19546
日期 05/08/2014
状态 Archive
Type 综合文章
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