When using ChipScope Pro Analyzer, I get unexpected results. My waveform is wrong (different than an external logic analyzer for instance). Why?
There are 2 mains reasons of such behavior:
1. Timing constraints are not met.
When you insert ChipScope in a design, you will increase your minimum clock period. Make sure, using Timing Analyzer after Place and Route, that you still meet your timings. You should also check for unconstrained paths in the design that are not controlled by timing constraints.If you try running ChipScope Analyzer, even if your timings are not met, you will get unexpected results.
2. During the insertion, "Disable JTAG clock BUFG insertion" has been selected.
This can also affect the timing on TCK (JTAG clock), and can produce the wrong waveform. We strongly recommend that you do not disable the JTAG clock BUFG insertion, even if it takes more resources (one more BUFG).
** This applies to designs on 10.1 or earlier. BUFG insertion is automatic from 11.1 forward.