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AR# 19664

6.2 EDK SP2 - EDK_BSB - Assigns incorrect clock pin LOC constraints for Insight V2P7-FF672


Keywords: UCF, sys_clk

Urgency: Standard

General Description:
When I create a MicroBlaze system using EDK 6.2 SP2 and the Base System Builder with Insight V2P7-FF672 board, the system clock is LOC'ed to E13 instead of D13. If I do not have an oscillator installed in the socket, the system will not have a clock. This problem occurs when I select certain IPs from BSB GUI list.

The following steps recreate this issue:
1. Run BSB.
2. Select Memec Design.
3. Select Virtex-II Pro P7-ff672 with P160 Comm module.
4. Select "2" for revision.
5. Select 50 MHz for Processor Clock Freq and On-chip H/W debug module for debug I/F (LMB BRAM=32 KB).
6. Select RS232, LEDs_4Bit, Push_Buttons_3Bit, DIP_Switches_8Bit, and deselect everything else for IP.
7. Finish BSB.

After performing these steps, you should see that sys_clk is LOC'ed to E13 ( by default, it should be D13).


To resolve this issue, change the pin assignment from E13 to D13.
AR# 19664
日期 04/10/2007
状态 Archive
Type 综合文章