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AR# 1972

Foundation Express 2.0.x: multiple modules in Foundation schematic can cause RLOC error:x4kma:312 in MAP

Description

Keywords: FPGA Express, Foundation, Express, schematic, U_SET, x4kma:312

Urgency: Standard

General Description:
Express has the ability to create modules (click the "Do Not Insert I/O"
button). The modules can be brought into Foundation (or any other schematic
entry tool) to be used in a top-level schematic. See (Xilinx Solution 3301)
for information on how this is done in Foundation.

However, if the Express module contains arithmetic functions or other functions
that use relative location constraints (RLOCs), a problem may occur. If
multiple calls to the same Express macro are done in a single design, then MAP
will issue an error similar to the following:


ERROR:x4kma:312 - The following symbols could not be constrained to a single
CLB:
CY4 symbol "U2/C4_C0_C1" (output signal=U2/C4_N2)
CY4_20 symbol "U2/C4_C0_C2" (output signal=U2/C4_C0_N7)
DFF symbol "U2/q_reg<0>" (output signal=&__A__16)
FMAP symbol "U2/FMAP_0" (output signal=U2/N54)
CY4 symbol "U1/C4_C0_C1" (output signal=U1/C4_N2)
CY4_20 symbol "U1/C4_C0_C2" (output signal=U1/C4_C0_N7)
There is more than one carry logic symbol associated with this CLB. These
symbols share the same RLOC attribute value, which requires them to be mapped
to the same CLB.


The issue here is that Express uses U_SETs instead of HU_SETs. Express groups
RLOC sets by giving them all the same U_SET name. This is required to isolate
multiple RLOC sets in one XNF file.

However, if multiple macros are used in a single design, the U_SET parameters
will link RLOC sets across multiple XNF files, and RLOC conflicts will occur.
There is nothing to uniquify the different calls to the same module.

解决方案

The solution is to edit the XNF file. Open the XNF created by Express in your
favorite text editor. Globally search for "U_SET" and replace each instance
with "HU_SET".

The HU_SET parameter will isolate the RLOC group within the single XNF file,
and will not attempt to combine sets with the same names across hierarchical
boundaries.

For more information about RLOCs and set parameters (H_SET, U_SET, and HU_SET),
please consult pages 4-79 through 4-97 of the Xilinx Libraries Guide.
AR# 1972
创建日期 02/28/1997
Last Updated 04/27/2007
状态 Archive
Type 综合文章