UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19726

6.3i NetGen, Timing Simulation - A simulator reports hold violations when simulating Virtex-4 designs with SRL16E components

描述

Keywords: timing, simulation, SimPrim, ERROR, ModelSim, NC-VHF, NC-Verilog, hold, error, Virtex-4, VCS

Urgency: Standard

General Description:
Back-annotated simulations of Virtex-4 designs containing SRL16E components report hold violations.

解决方案

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19726
日期 11/10/2008
状态 Archive
Type 综合文章
的页面