UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19728

6.3i NetGen, Timing Simulation - NetGen is not writing out INIT attributes for ODDR and IDDR if non-default values are used

描述

Keywords: timing, simulation, SimPrim, ERROR, ModelSim, NC-VHDL, NC-Verilog, Virtex-4, VCS, ODDR, IDDR, INIT, attribute

Urgency: Standard

General Description:
When I use non-default values, NetGen does not write out INIT attributes for ODDR and IDDR. This prevents back-annotated models from compiling.

解决方案

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19728
日期 11/10/2008
状态 Archive
Type 综合文章
的页面