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AR# 19729

6.3i NetGen, Timing Simulation - The SRTYPE value is set as SYNC for ODDR and IDDR, even though it is set as ASYNC in the HDL code


Keywords: timing, simulation, SimPrim, ERROR, ModelSim, NC-VHDL, NC-Verilog, Virtex-4, VCS, SRTYPE, SYNC, ASYNC, ODDR, IDDR

Urgency: Standard

General Description:
The SRTYPE value is set to SYNC for ODDR and IDDR components, even though I changed this to ASYNC in the HDL code.


This problem has been fixed in the latest 6.3i Service Pack available at:
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19729
日期 11/10/2008
状态 Archive
Type 综合文章