UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19862

6.3i UniSim, Simulation - The ISERDES and OSERDES models report different messages when incorrect attributes are used

描述

Keywords: UniSim, simulation, ModelSim, NC-VHDL, ISERDES, OSERDES, Virtex-4

Urgency: Standard

General Description:
The ISERDES and OSERDES models report different messages for the same condition. For example, when I set DATA_RATE as DDR and DATA_WIDTH = 2 for ISERDES and OSERDES, I receive the following messages:

OSERDES:
==========
# ** Warning: WARNING : DATA_WIDTH or DATA_RATE has illegal values.
# Time: 10 ps Iteration: 0 Instance: /oserdes_vhd_tb/uut/u1/inst_ioout

ISERDES:
==========
# ** Failure: Attribute Syntax Warning The attribute DATA_WIDTH on /ISERDES instance is set to 2.
# The Legal values for DDR mode are 4, 6, 8, or 10
# Time: 0 ps Iteration: 0 Process: /iserdes_vhd_tb/uut/u1/prcs_init File: unisim_VITAL.vhd
# Break at unisim_VPKG.vhd line 1328

Also, the severity levels of the messages are completely opposite.

解决方案

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19862
日期 11/18/2008
状态 Archive
Type 综合文章
的页面