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AR# 19884

4.2i NGD2VHDL, Timing Simulation - The bit order of busses gets reversed in the back annotated netlist


Keywords: 4.2i, bus, reverse, timing, simulation, back, annotated, netlist

Urgency: Standard

General description:
If I have a bus coded as (X to Y) and I run ngd2vhdl on the implemented design, in the timing simulation model the bus declaration changes to (Y downto X).

As a result, the simulation does not work correctly.


This is a problem in ISE4.2i and earlier releases. The issue can be worked around by changing the bus-ordering from (X to Y) to (Y downto X) in the design. This way when the back annnotation is done, it will match correctly.

This problem is fixed in ISE5.1i
AR# 19884
日期 08/11/2005
状态 Archive
Type 综合文章