UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19890

6.3i XST - XST incorrectly synthesizes particular VHDL decoders

描述

Keywords: XST, decoder, VHDL, case, with, select, if, elsif, FPGA

XST incorrectly synthesizes these particular VHDL decoder:

with div select
an <= "1110" when "00",
"1101" when "01",
"1111" when "10",
"1111" when others;

with div select
an <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"1111" when others;


XST gives as a result:

an="1011" when div="10"
an="0111" when div="11"

You will get similar problems with "case" or "if ... elsif" statements.

解决方案

This issue is fixed in ISE 7.1i.

To work around the issue with ISE 6.3:

1. You can comment the line "1111" when "10".
2. You can use a "case statement".
3. You can turn off the XST option "decoder extraction".
AR# 19890
日期 01/07/2009
状态 Archive
Type 综合文章
的页面