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AR# 19934

10.1 Floorplan Editor/ PACE Virtex-4/Virtex-5 - DSPs and FIFOs are included in the Area Group when not in the design

描述

When I place an area constraint or group in PACE, the UCF constrains the RANGE constraints for FIFOs and DSPs. My design does not include DSPs or FIFOs, so I am not sure why these constraints are in the UCF. When is this going to be fixed?

解决方案

To work around this issue, manually modify the UCF and remove the RANGE constraints for the DSPs and FIFOs. If you create an Area Group that covers FIFOs and DSP48s, they are filled so that they are part of the slice logic in the Area Group; however, these elements are not included. 

 

This is scheduled to be fixed in the next major design tools release.

AR# 19934
日期 05/16/2014
状态 Archive
Type 综合文章
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