We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19955

6.3i PrimeTime/NetGen - SDF causes PrimeTime annotation issue due to the pulse width check


Keywords: path pulse, min_pulse_width

Urgency: Standard

General Description:
When I run the SDF and Verilog files from NetGen, I receive the following annotated issues from PrimeTime:

"Warning: 8982 WIDTH had no corresponding timing arc in the library, and are converted into user min_pulse_width."

"Warning: SDF construct 'PATHPULSE' ignored (44283 occurrences)."

When is this going to be fixed?


This problem has been fixed in the latest 6.3i Service Pack available at:
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19955
日期 03/27/2007
状态 Archive
Type 综合文章