AR# 19977

6.3 EDK, NC-Sim - EDK/NCSim behavioral simulation issues the warning: "ncelab: *W,CUNOTB: component instance is not fully bound..."


Urgency: Hot

General Description:

As noted in the EDK 6.3 Release Notes, there are issues with simulating some EDK processor system cores in EDK. During elaboration, the following warning occurs:

"ncelab: *W,CUNOTB: component instance is not fully bound ({*Name Protected*})."

Also, the behavioral simulation does not function properly and does not match gate-level simulations.


Because some Xilinx processor cores lack the library "use" statement, ncelab cannot always bind to the correct underlying entities. When the wrong entity is binded, the design might not behave as expected. To resolve the elaboration warnings, the VHDL code must be modified to include library "use" declarations for all libraries referenced in each core's (and each underlying core) ".pao" file. To modify the cores, follow these steps:

1. Copy each core and the cores it depends on to a "pcores" directory. See (Xilinx Answer 20069) for more information on creating local copies of the cores.

2. Edit each VHDL file to include a library "use" statement for each library cited in the "data/.pao" file such as the following for the PLB2OPB bridge:

.pao file


lib proc_common_v1_00_b mux_onehot

lib plb2opb_bridge_v1_01_a plb2opb_bridge_srl16x30


Add the following to each ".vhd" file in "/src/vhdl" for the PLB2OPB core:

library plb2opb_bridge_v1_01_a;

use plb2opb_bridge_v1_01_a.all;

library proc_common_v1_00_b;

use proc_common_v1_00_b.all;

3. Clean and generate the simulation models. Make sure there are none of the above elaboration errors relating to the EDK system. However, some cores are encrypted and cannot be fixed manually. Xilinx is working to fix these cores so they will bind correctly. Most encrypted cores will be fixed in EDK 6.3, Service Pack 2 scheduled for release in December 2004. For more information, contact the Xilinx Hotline.
AR# 19977
日期 03/16/2012
状态 Archive
Type 综合文章