PAR cannot place the Complementary Single-Ended (CSE) differential DCI I/O in the same bank as the non-differential DCI of the same I/O Standard.
For example, a DRC error occurs in PAR if DIFF_HSTL_II_DCI and HSTL_II_DCI are in the same bank.
This issue applies to the following:
DIFF_SSTL2_II_DCI vs SSTL2_II_DCI
DIFF_SSTL18_II_DCI vs SSTL18_II_DCI
DIFF_HSTL_II_DCI vs HSTL_II_DCI
DIFF_HSTL_II_DCI_18 vs. HSTL_II_DCI_18
The DRC error is incorrect. This issue will be fixed in ISE 8.1i, scheduled for release in August 2005.
You can work around this issue as follows:
1. Constrain all input and output that require the differential HSTL/SSTL DCI standard as it should be.
NET "<netname>" LOC="<pin_location>" | IOSTANDARD = DIFF_HSTL_II_DCI_18; # ucf constraint
2. Constrain all single-ended input and output that require HSTL/SSTL DCI standard using the non-DCI IOSTANDARD. This is a temporary assignment and must be changed later after PAR has completed.
NET "<netname>" LOC="<pin_location>" | IOSTANDARD = HSTL_II_18;
3. Implement the design in ISE (synthesis, NGDBuild, MAP and PAR).
4. Once PAR is completed, use FPGA Editor to edit the single-ended I/Os and use HSTL_II_DCI_18 instead of HSTL_II_18 for the ones that require single-ended DCI.
5. Save the modified NCD/PCF.
6. Run "bitgen -d <normal options>" on the modified NCD/PCF. The "-d" option forces BitGen to ignore the DRC check.