UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19997

6.3i UniSim, Simulation - FIFO16 UniSim model is not asserting the ALMOST_EMPTY flag when writing to the FIFO (Verilog)

描述

Keywords: ModelSim, NC-VHDL, Virtex-4

Urgency: Standard

General Description:
When the FIFO16 model is being written to and the ALMOST_EMPTY_OFFSET threshold is met, the ALMOST_EMPTY flag should de-assert. The ALMOST_EMPTY flag is not de-asserting in a Verilog UniSim simulation. Why is this occurring?

解决方案

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 3.
AR# 19997
日期 10/16/2008
状态 Archive
Type 综合文章
的页面