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AR# 20007

6.3i UniSim, SimPrim, Timing - Incorrect output on DOA/B of the RAMB16 is seen in simulation (Verilog)


Keywords: simulate, Virtex-4, zero, DOB, behavioral, outputs, unexpected

Urgency: Standard

General Description:
When running a behavioral or timing simulation with the Virtex-4 RAMB16, the outputs of the RAMB16 are all zero or not the expected outputs.


One condition where this has been seen is if the SSRA and SSRB inputs are not driven. If you are not using these ports in your design, they should be tied to zero. If these inputs are not driven, you will see zeros on the output of your data for that port.

Also, be sure that the correct address bits are being used. The ADDRA and ADDRB pins on the RAMB16 are 15-bits wide; however, the valid addresses for non-cascadable block RAM are found only on pins 13 to pins (14 - address width). ADDRA/B[14] is only used in cascade mode.
AR# 20007
日期 10/16/2008
状态 Archive
Type 综合文章