AR# 20083

6.3i IP Update #4 CORE Generator - Release Notes and Known Issues for CORE Generator 6.3i IP Update 4 (IP4_G)


General Description:

This Answer Record contains Release Notes for 6.3i IP Update #4 (also known as IP4_G) and includes the following:

- Software and Tool Requirements

- Installation Instructions

- MXE Simulation Library

The following IPs are included in this IP Update release.

NOTE: For the Release Notes and Known Issues for the individual IPs, refer to the linked Answer records below:

- Release Notes and Known Issues for GFP v1.2 (Xilinx Answer 20275)

- Release Notes and Known Issues for SPI-4.2 v7.1 (Xilinx Answer 20274)

- Release Notes and Known Issues for Fifo Generator v2.0 (Xilinx Answer 20219)

- Release Notes and Known Issues for Content Addressable Memory (CAM) v5.1 (Xilinx Answer 20218)

- Release Notes and Known Issues for 8b/10b Decoder v7.0 (Xilinx Answer 20217)

- Release Notes and Known Issues for Asynchronous FIFO v6.1 (Xilinx Answer 20216)

- Release Notes and Known Issues for all PCI 32, PCI64, and PCI-X products (Xilinx Answer 20285)

- Release Notes and Known Issues for Embedded Tri-mode Ethernet MAC Wrapper v1.0 (Xilinx Answer 20193)

- Release Notes and Known Issues for Fibre Channel v1.0 (Xilinx Answer 19527)

- Release Notes and Known Issues for Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 (Xilinx Answer 19880)

- Release Notes and Known Issues for Aurora v2.2 (Xilinx Answer 14443)

- Release Notes and Known Issues for Gigabit Ethernet MAC v5.0 (Xilinx Answer 19878 )

- Release Notes and Known Issues for Tri-Mode Ethernet MAC v1.1 (Xilinx Answer 19882)

- Release Notes and Known Issues for 10 Gigabit Ethernet MAC v5.0 (Xilinx Answer 19879)

- Release Notes and Known Issues for XAUI v5.0 (Xilinx Answer 19881)

- Release Notes and Known Issues for all DSP products (Xilinx Answer 20289)

DSP cores included in this release are:

............XFFT v3.1

............Complex MPY v2.0

............MAC FIR v5.1

............RS Decoder v5.1

............Viterbi Decoder v5.0

............3GPP/UMTS TCC Encoder v1.0

............3GPP/UMTS TCC Decoder v1.0


Supported Operating Systems

Windows 2000 Professional (Service Pack 2 to 4)

Windows XP Home (Service Pack 1)/Professional (Service Pack 1)

Sun Solaris 8/9

Red Hat Linux 7.3/8.0

Tool Requirements

To use this IP Update, first ensure that you have installed ISE 6.3i with Service Pack 2 (6.3.02i) or later. ISE 6.3i Service Packs can be downloaded from this page:

Acrobat Reader Requirement

Acrobat Reader Version 5 or later must be installed to view core data sheets. You can download the latest Acrobat software from the following Adobe site:

To search for other available IP cores, please see:

If you have comments, questions, or problems, please contact Xilinx Technical and Applications Support at:

Install the IP Update using one of the following methods:

Method 1: Automated Update using the Updates Installer

1. Start the CORE Generator Update Installer (from the CORE Generator Main GUI, select Tools -> Update Installer).

If you are prompted for a proxy host, contact your administrator to determine the proxy host address and port number that you should be using to get through your firewall.

2. Select " 6.3i IP Update 4" from the list of updates in the Available Packages panel.

3. Click "Add To Install Queue" to add the ZIP file for the update to the install queue.

If you are prompted to enter a log-in name and password, use the Xilinx log-in and password that you would normally use when downloading IP Updates and software Service Packs.

4. Click "Install All Packages From Queue" to automatically initiate a download of the update.

After the update is downloaded, the Updates Installer displays a dialog box indicating that it is terminating the CORE Generator session and installing the downloaded archive. Another dialog box will inform you when the update installation is complete; you can then restart CORE Generator.

5. To confirm that you have installed the update properly, check the following file:


NOTE: This step assumes that your Xilinx software is installed in C:\Xilinx.

Method 2: Manual Installation Method

1. Close the CORE Generator application if it is running.

2. Download the ZIP file (PC) or "tar.gz" file (UNIX) from the following location and save it to a temporary directory:

NOTE: Before you can access this page and the files listed on it, you must be registered for CORE Generator IP Updates access.

For Windows, unzip the ZIP file using WinZip 7.0 SR-1 or later.

For UNIX, you can use UnZip to unpack this ZIP file. Xilinx recommends that you download the "tar.gz" file and unpack it using the UNIX command line gunzip and tar utilities. WinZip and GNU tar are not recommended for extracting the 'tar.gz" archive because of differences in the way they handle files with long path names. Please see (Xilinx Answer 11162) for more details.

3. Extract the ZIP file ( or "tar.gz" (63i_ip_update4.tar.gz) archive to the root directory of your Xilinx software installation. Allow your extractor utility to overwrite all existing files and maintain the directory structure pre-defined in the archive.


The Xilinx software installation directory is typically located at "C:\XILINX" if the installation defaults were used. You can verify the location of the Xilinx install by entering the following on the DOS command line:

echo %XILINX%


If you have already installed your Xilinx ISE software, the Xilinx installation directory location is the value of the XILINX variable, which is defined by your setup script. After sourcing your Xilinx setup script, enter the following to determine the location of your Xilinx installation:

echo $XILINX

You might need system administrator privileges to install the update.

4. Restart CORE Generator. During start-up, CORE Generator automatically detects that new IP has been added to your installation. It allows you to specify which IP customizers (cores) will be visible in your currently active CORE Generator project. For your current project, you can select the following:

- Display only the latest versions for "All" cores in the catalog.

- Update the catalog view to add only "New" cores to the display.

- Make a "Custom" selection of cores visible in the CORE Generator catalog display for your current project.

5. Determine whether the installation was successful by verifying that the new cores are visible in the CORE Generator GUI.

MXE Simulation Library

The cores delivered with this IP Update require updated XilinxCoreLib libraries; please see (Xilinx Answer 10616) on how to obtain the latest pre-compiled MXE libraries.
AR# 20083
日期 07/28/2010
状态 Archive
Type 综合文章