We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20119

8.1 EDK, XMD - XMD breaks up PLB/OPB byte/half-word mwr/mrd transactions on PowerPC into multiple single-byte transactions


XMD splits up half-word transactions into 2 single-byte transactions on the PLB/OPB. This is unnoticed when accessing many peripherals such as on-chip block RAM in which two single-byte transactions are correctly masked. Due to this, a mwr/mrd command using the 'h' transaction size qualifier for half-word transfers in XMD will not be equivalent to a 'short' type access to a memory mapped I/O in C-code.

How do I work around this issue?


Perform the same operations using 'short' data types or XIO_In16 and XIO_Out16 functions in C-code. Note that single-byte and full-word XMD operations are performed correctly in one transaction.

This has been fixed in EDK 7.1. Note that the XMD debugconfig -memory_datawidth_matching enable command should be used for byte and half-word transactions to be bus accurate as it is not enabled by default.

In EDK 8.1i the debugconfig -memory_datawidth_matching enable will be enabled by default, thus the user does not need to use this command when doing byte or half-word transactions.

In EDK 8.2i the debugconfig -memory_datawidth_matching enable will be removed such that whatever type operation (word/half/byte) is requested.

"mrd <addr> 1 b" -> Does Byte transfers

"mrd <addr> 1 h" -> Does Halfword transfers

"mrd <addr> 1 w" -> Does word transfers (also the default).

Each operation will be preformed in a single transaction.

AR# 20119
日期 12/15/2012
状态 Active
Type 综合文章