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AR# 20203

6.3 System Generator for DSP - Why do I see a mismatch between the System Generator simulation and the VHDL behavioral simulation when using the FIFO Block with type "Embedded FIFO" (FIFO16)?

描述

General Description: 

Why do I see a mismatch between the System Generator simulation and the VHDL behavioral simulation when using the FIFO Block with type "Embedded FIFO" (FIFO16)?

解决方案

This is a known issue with the FIFO16 VHDL UniSim model. The UniSim almost empty and almost full offset settings offset the correct setting by one clock, causing mismatches in both behavioral and post-translate simulations. This has been fixed in ISE 6.3, Service Pack 1.

AR# 20203
日期 05/16/2014
状态 Archive
Type 综合文章
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