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AR# 20206

7.1 System Generator for DSP - Why do I get an error in Synplify when synthesizing with HDL Language set to Verilog and using the FIFO Block with type "Embedded FIFO" (FIFO16)?

描述

Why do I get an error in Synplify when synthesizing with HDL Language set to Verilog and using the FIFO Block with type "Embedded FIFO" (FIFO16)?

解决方案

This problem is due to the way the "defparam" parameters are written in the Verilog code. 

 

You can work around the problem by using XST. 

 

This problem has been fixed in System Generator for DSP 8.1.

AR# 20206
日期 05/16/2014
状态 Archive
Type 综合文章
的页面