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AR# 20222

PowerPC SmartModel - Message: "** Note (SmartModel): UTLB has been flash invalidated"


Keywords: PPC405, simulation, timing, memory model, UniSim, SimPrim, UTLB, Flash, invalidated, SWIFT, EDK, simulate

I am running a simulation with the PowerPC, and the following message occurs:

"# ** Note (SmartModel):
# UTLB has been flash invalidated
# Time: 77050000 ps Instance:/ppc_tbtop/i0/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst"

What does this message mean, why does it occur, and how can it be resolved?


The PowerPC SmartModel issues this message stating that the unified "translation look-aside buffer" (TLB) is being invalidated. For more information on the TLB, see the "Virtual-Memory Management" chapter of the "Power PC Processor Reference Guide" (UG011) at:

To access this guide, select "See All User Guides".

The PowerPC issues the message, "UTLB has been flash invalidated," when an input to the PowerPC Core is in an unknown state.

This message might occur during functional, structural, or timing simulations, or when using an external memory model that has timing checks or timing information, from a third-party vendor for an embedded PowerPC simulation.

You can resolve this issue when running a functional or structural simulation, in which timing is not a concern, by turning off timing checks in the simulator. Refer to the vendor documentation for more information.

If you are running a timing simulation using memory models with timing information, set up and hold times might have been violated and must be addressed. Check the timing of your design to make sure the proper constraints were used and that the design is meeting timing.
AR# 20222
日期 10/16/2008
状态 Archive
Type 综合文章