We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20273

LogiCORE FIFO Generator v2.0 - Simulation Failure (PROG_EMPTY) for FIFO16-based FIFO


General Description: 

When using Fifo16 based FIFO, the PROG_EMPTY might fail to be asserted. This can be seen in Verilog and VHDL behavioral simulation.


The FIFO Generator GUI automatically calculates valid ranges for Programmable Empty Assert and Negate Thresholds on page 2 of the GUI, depending on values specified on the page 1 of the GUI. 


When using a FIFO16-based FIFO Generator and when the "Output Depth" specified by the user on page 1 is equal to, or less than, the "Primitive Depth" selected, the ranges provided on page 2 will be incorrect. 


In particular, the ranges calculated by the GUI will allow the user to select a programmable empty threshold which is equal to the "Output Depth" under these conditions. If the programmable empty assert or negate threshold is set to be equal to the output depth, the PROG_EMPTY will not be asserted.  


To work around this issue, manually specify the desired threshold based on the appropriate "output depth".

AR# 20273
日期 05/16/2014
状态 Archive
Type 综合文章