This Answer Record contains the Release Notes for the SPI-4.2 Core v7.1, released in 6.3i IP Update #4, which includes the following:
- New Features in v7.1
- Bug Fixes in v7.1
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 20083).
New Features in v7.1
There are no new features in this release.
Bug Fixes in v7.1
- TStat[1:0] signals use IBUFGDS when using LVDS status I/O. (Xilinx Answer 19105)
- Synplify fails to synthesize a Verilog wrapper file; an NGDBuild error occurs. (Xilinx Answer 20012)
- Does the Xilinx SPI-4.2 Core support 622 Mbps? (Xilinx Answer 20024)
- When I simulate the VHDL demonstration testbench, a "value out of range" error occurs. (Xilinx Answer 20028)
- When a SPI-4.2 v7.0 Core is generated, the resulting Source core netlist was not synthesized with the chosen clocking option. (Xilinx Answer 20318)
- Version 7.1 of the SPI-4.2 Core supports only the Virtex-4 family. For Virtex-II and Virtex-II Pro designs, use the v6.x SPI-4.2 Core, available from the SPI-4.2 IP lounge.
- Version 7.1 Core is compatible with ISE 6.3i. For compatibility with ISE 7.1i, see (Xilinx Answer 20486).
- Migrating from v6.1 to v7.1. (Xilinx Answer 20036)
- When using Dynamic Phase Alignment or the SPI Core, RDClk must be running at least 220 MHz minimum.
Core Generation Issues
- The Regional Clocking option should not be valid when generating a slave Source core. (Xilinx Answer 20001)
- When I generate an SPI-4.2 (PL4) Core through CORE Generator, the following errors occur:
"ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\5_2i\pl4_core.asy does not exist."
"ERROR: Did not generate ISE symbol file for core <pl4_core>." (Xilinx Answer 15493)
Constraints and Implementation Issues
- When I run an implementation tool with an SPI-4.2 Core, several NGDBuild WARNING and INFO messages are reported. (Xilinx Answer 20000)
- RDClk180_GP, SysClk180_GP, and SysClk180_GBSLV are no longer used. (Xilinx Answer 20023)
- When I run a PAR of the implementation phase, a "PAR:276" warning appears. (Xilinx Answer 20037)
- Placement failures occur in PAR when the SPI-4.2 FIFO Status signals' I/O Standard is set to LVTTL I/O. (Xilinx Answer 20280)
- Timing Analyzer (TRCE) reports "0 items analyzed." (Xilinx Answer 20040)
- "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported." (Xilinx Answer 19999)
- When running implementation, undefined I/O (single-ended) defaults to LVCMOS causing WARNINGS in NGDBuild. (Xilinx Answer 20319)
- The SPI-4.2 Core signals default to LVDS without the internal device termination. If internal termination is needed, it must be defined in the UCF. In v7.1, this is predefined in the "wrapper.ucf" file. However, it needs to be uncommented. For a complete list of supported I/O, see (Xilinx Answer 20017).
General Simulation Issues
- Running "simulate_mti.do" or compiling design example files gives error. (Xilinx Answer 20616)
- Using Dynamic Phase Alignment, PhaseAlignComplete signal is not asserted and SnkOof never gets de-asserted. (Xilinx Answer 20282)
- Running the "gen_sim_model" script causes: "WARNING:NgdBuild:440 - FF primitive 'U0/clkdomain0/srts/output_ff' has unconnected net." (Xilinx Answer 20018)
- In timing simulation, TDat and TCtl become "x" right after reset. (Xilinx Answer 20015)
- The Sink Core never goes in frame (SnkOof ="1") due to an incorrect training pattern sent from the Xilinx Source core. (Xilinx Answer 20016)
- When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behavior occurs. (Xilinx Answer 15578)
- When I run timing simulation in Verilog, the Core never goes in frame, signals go "x", or pulses are swallowed. (Xilinx Answer 9872)
- When I simulate an SPI-4.2 Core, multiple warnings appear at the beginning of the simulation. (Xilinx Answer 20030)
- During simulation, warning occurs: "Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK." (Xilinx Answer 20031)
- When post-NGDBuild simulation of the Sink and Source netlists is run, the initial contents of the calendar specified in the COE file are not used. (Xilinx Answer 20281)
- When targeting Virtex-4 design with SPI4.2, be advised of silicon issue. (Xilinx Answer 20796)
- When targeting Virtex-4 design with SPI4.2 v7.1 Core, you might notice the device does not function properly in the hardware. (Xilinx Answer 20303)
- When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations. (Xilinx Answer 20022)
- An SPI-4.2 (PL4) Sink Core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP4 error. (Xilinx Answer 15442)
- When I open the SPI4.2 GUI in COREGen using the Hardware timeout evaluation license, it displays a pop-up message. The message indicates that the Hardware timeout lasts for 6-8 hours. However, the core will run only 2 hours.
Other Helpful Answer Records
- What is the power consumption of SPI-4.2 Core? (Xilinx Answer 20430)
- How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM? (Xilinx Answer 15500)
- Which I/O Standards are supported for SPI-4.2 Core? (Xilinx Answer 20017)
- If you are using multiple SPI-4.2 Cores in a single device, see the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 User Guide.
SPI- 4.2 (PL4) v7.0 KNOWN ISSUES
The SPI-4.2 v7.0 Core is now obsolete. Please upgrade to the latest version of the core.
For information on existing SPI-4.2 v7.0 issues, see (Xilinx Answer 19981).