While targeting Virtex-4 designs with SPI4.2 v7.1 core, the device does not function properly in the hardware, and I receive errors similar to the following:
"SPI4.2 core not functioning reliably"
"SPI4.2 core not going in frame"
"TSClk or TDClk not being generated"
When I run a gate level or timing simulation, the following warning message occurs:
"# ** Warning: Attribute Syntax Warning The attribute FACTORY_JF on DCM_ADV instance * is set to 0000000000000000.
# Legal Values for this attribute are F0F0 hex when DLL_FREQUENCY_MODE is set to HIGH and C080 hex when DLL_FREQUENCY_MODE set to LOW"
The problem is related to an incorrect or missing FACTORY_JF attribute for the DCM that generates TSClk and TDClk in the source core.
If you are using Source core in MASTER mode, add the following constraint to your UCF file and re-run the implementation:
INST "<src_instance_name>/U0/clk0/tsd" FACTORY_JF = "C080" ;
If you are using Source core in SLAVE mode, add the following two constraints to your UCF file and re-run the implementation:
INST "pl4_src_clk0/tsclk_dcm0" FACTORY_JF = "C080" ;
INST "pl4_src_clk0/tdclk_dcm0" FACTORY_JF = "F0F0" ;
You might need to replace "pl4_src_clk0" above with the actual instance name of your clocking module.
This issue has been fixed in SPI4.2 v7.2 core. If possible, upgrade to the latest core.