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AR# 20316

LogiCORE 2-D Discrete Cosine Transform (DCT) v2.0 - Why does the 2-D DCT VHDL model only simulate at clock speeds over 100 MHz?

描述

Keywords: COREGen, CORE, CORE Generator, 2-d, DCT, simulation, VHDL, 100 MHz

Why does the 2-D DCT VHDL model only simulate at clock speeds over 100 MHz?

解决方案

The way the model is currently written, it is expecting a clock that is a minimum of 100MHz.

This issue is being investigated and will be fixed or documented in a future release.
AR# 20316
日期 07/26/2007
状态 Archive
Type 综合文章
的页面