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AR# 20322

v2.2 Aurora Reference Design - Release Notes and Known Issues


General Description: 

What new features are included in the v2.2 Aurora Reference Design? How does it differ from previous versions v1.3 and v2.1?


Following is a list of important differences between v2.2 and v1.3/v2.1. 


New Features 

- Size: the new designs use significantly fewer resources  

- Flexibility: the newest release (version 2.2) includes Simplex channels (uni-directional MGT connections that allow better resource utilization), as well as a new user interface option. This new option is a stripped down version of the LocalLink interface that you can select to write words to an infinite frame.  

- Clock Correction: the new designs allow clock correction to be customized or disabled. 

- Device support: the older designs support only Virtex-II Pro. The new designs also support Virtex-II Pro X, and will support Virtex-4. 


Bug Fixes 

- Non-compliant verification sequence: the old 201 will connect to another old 201, but not to other Aurora standard single-lane designs. 

- False resets: the 804 v1.3 design can reset itself if it recognizes a very specific data pattern (which it interprets as a non-word aligned initialization character sent from the other side). 

- DCM consumed: the old clock modules consume a DCM, even when one is not needed 


NOTE: Xilinx recommends using version 2.2 if you are a new Aurora user. 


If already using one of the old designs, keep the following in mind: 

- The interface is the same. The only change is the addition of the clock correction interface; you can simply connect it to the clock correction module provided with the design.  

- Xilinx recommends upgrading if using an 804 or a 201 in a non-closed system because of the bug fixes in the newest release. 

- If the design is working and the bug fixes, resource costs, and portability of the design are not a concern, there should be no issues with continuing to use the old version.

AR# 20322
日期 05/16/2014
状态 Archive
Type 综合文章