What are valid remainder values when transmitting data using the RapidIO serial or parallel physical layer cores?
In the TX direction, data on lnk_td must be 16 bit aligned. The core will then align the packet to the 32 bit boundary and send it across the link. The core always has to add 8 bits of header (S(1),ACKID(3), RSVD(1), RSVD(2)) and 16 bits of CRC to each outgoing packet. The core then has the option of adding 16 bits of padding in order to align the packet to a 32 bit boundary.
So lnk_trem[0:2] values of 1, 3, 5 and 7 (which means 2, 4, 6 and 8 bytes are valid) causes an illegal alignment. The core has no way of aligning to a 32 bit boundary since it must add 1 byte of header and then can add only 2 bytes of padding at a time.