UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20574

CPLD CoolRunner-II - What is the minimum/maximum input frequency for the clock divider?

描述

What is the minimum and maximum input frequency for the clock divider?

解决方案

The clock divider is not PLL or DLL based, so there is no minimum clock frequency nor is a constant clock source required.

The minimum input of the parameter global clock pulse width, High or Low (TCW), is defined. These minimum inputs are then used to determine a minimum cycle time and frequency.

For example :

XC2C256-7 Tcw = 2.2ns

The maximum clock divider input frequency = 1/(2.2ns + 2.2ns) = 227 MHz

AR# 20574
日期 12/15/2012
状态 Active
Type 综合文章
的页面