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AR# 20623

6.3.p03 System Generator for DSP - How can I reduce the fanout on the clock enable logic to decrease the routing delays?

描述

General Description: 

How can I reduce the fanout on the clock enable logic to decrease the routing delays?

解决方案

In System Generator 6.3.p03, additional pipeline registers have been added to the output of the clock enable generation logic. These additional registers can be used by synthesis tools to reduce fanout and make it easier to route clock enable signals for high speed designs. For more information, see: 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20623
日期 05/19/2014
状态 Archive
Type 综合文章
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