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AR# 20624

6.3.p03 System Generator for DSP - Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

描述

General Description: 

Why do I get a simulation mismatch when using the Delay Block retiming option in my Verilog design?

解决方案

This has been fixed in System Generator 6.3.p03. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20624
日期 05/19/2014
状态 Archive
Type 综合文章
的页面